The chip is a 64 bit chip, yet, the PAE is only 36-bits. This means it could support a max of 24 GB of memory? Ridiculous! Essentially, you have a bottle neck because the PAE will not let you use up to 64 bits of data from memory at a time which is the potential of a 64 bit chip could address, right?
But, wait. The TLBs (memory controller) control the logical address set by the PAE. So, eventhough though your CPU can generate 36-bits of logical addresses, it doesn't mean that the memory controller is also limited to 36 bits. It can be 64 bits memory controller because the memory controller controls the page tables, and segment tables.
Why didn't they make the chip support full 64 bit?