The POWER7 is a multi-core processor, available with 4, 6, or 8 cores. There is also a special TurboCore mode that can turn off half of the cores from an eight-core processor, but those 4 cores have access to all the memory controllers and L3 cache. This makes each core's performance higher which is important for workloads which require the fastest cores possible.
Each core is capable of four-way simultaneous multithreading (SMT). The POWER7 has approximately 1.2 billion transistors and is 567 mm2 large fabricated on a 45 nm process. A notable difference from POWER6 is that the POWER7 executes instructions out-of-order instead of in-order. Despite the decrease in maximum frequency compared to POWER6 (4.25 GHz vs 5.0 GHz), each core has higher performance than the POWER6, while having up to 4 times the number of cores.
POWER7 has these specifications:
45 nm SOI process, 567 mm2
1.2 billion transistors
3.0 – 4.25 GHz clock speed
max 4 chips per quad-chip module
4, 6 or 8 cores per chip
4 SMT threads per core (available in AIX 6.1 TL05 (releases in April 2010) and above)
12 execution units per core:
2 fixed-point units
2 load/store units
4 double-precision floating-point units
1 vector unit supporting VSX
1 decimal floating-point unit
1 branch unit
1 condition register unit
32+32 kB L1 instruction and data cache (per core)
256 kB L2 Cache (per core)
4 MB L3 cache per core with maximum up to 32MB supported. The cache is implemented in eDRAM, which does not require as many transistors per cell as a standard SRAM so it allows for a larger cache while using the same area as SRAM.
This gives the following theoretical performance figures (based on a 4.14 GHz 8 core implementation):
max 33.12 GFLOPS per core
max 264.96 GFLOPS per chip
POWER7 held during 3 1/2 months the TPC-C top result with 10,366,254 tpmC. Using a 780 server with 24 CPUs (192 cores) out of a possible 32 CPUs (256 cores) running at 3.86 GHz.